1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor devices and to chemical mechanical polishing and planarization of semiconductor devices.
2. Background of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology has placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
In order to further improve the current density of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity for conductors and materials having low dielectric constant (low k, defined herein as having dielectric constants, k, less than about 4.0) as insulating layers to reduce the capacitive coupling between adjacent interconnects. Increased capacitative coupling between layers can detrimentally affect the functioning of semiconductor devices.
One conductive material gaining acceptance is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 xcexcxcexa9-cm compared to 3.1 xcexcxcexa9-cm for aluminum), and a higher current carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern. Etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, i.e. vias, and horizontal interconnects, i.e., lines. Conductive materials, such as copper, and other materials, such as barrier layer materials used to prevent diffusion of conductive material into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess conductive material and excess barrier layer material external to the etched pattern, such as on the field of the substrate, is then removed.
Barrier layer materials include, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride.
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or xe2x80x9cpolishingxe2x80x9d a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in damascene processes to remove excess deposited material and to provide an even surface for subsequent levels of metallization and processing. Planarization may also be used in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing pad while dispersing a polishing composition to effect both chemical activity and mechanical activity.
Conventionally, in polishing copper features, such as a dual damascenes, the copper material is polished to the barrier layer, and then the barrier layer is polished to the underlying dielectric layer. One challenge which is presented in copper polishing is that the interface between copper and the barrier layer is generally non-planar. Further, the copper material and the barrier materials are often removed from the substrate surface at different rates. These challenges in copper removal often results in the retention of copper containing material, or residue, on the surface of the substrate. To ensure removal of all the copper material and residue before removing the barrier material, it is necessary to overpolish the copper and the interface. Overpolishing of copper and the interface can result in forming topographical defects, such as concavities or depressions, referred to as dishing, and can further lead to non-uniform removal of the barrier layer disposed thereunder.
FIG. 5 is a schematic view of a substrate illustrating the phenomenon of dishing. Conductive lines 211 and 212 are formed by depositing conductive material, such as copper or copper alloy, in a feature definition formed in the dielectric layer 210, typically comprised of silicon oxides or other dielectric materials. After planarization, for example, a portion of the conductive material is depressed by an amount D, referred to as the amount of dishing, forming a concave copper surface. Dishing results in a non-planar surface that impairs the ability to print high resolution lines during subsequent photolithographic steps and detrimentally affects subsequent surface topography of the substrate and device formation. Dishing also detrimentally affects the performance of devices by lowering the conductance and increasing the resistance of the devices, contrary to the benefit of using higher conductive materials, such as copper.
Therefore, there exists a need for a method and related CMP composition which facilitates the removal of copper containing material residue and the barrier layer, and provides selectivity therebetween and to the underlying dielectric layer.
The invention generally provides a method and composition for planarizing a substrate surface having a barrier layer disposed thereon. In one aspect, the invention provides for planarizing a substrate surface, comprising providing a substrate comprising a dielectric layer with feature definitions formed therein, a barrier layer conformally deposited on the dielectric layer and in the feature definitions formed therein, and a copper containing material deposited on the barrier layer and filling the feature definitions formed therein, chemical mechanical polishing the substrate with a bulk CMP composition to substantially remove excess copper containing materials, chemical mechanical polishing the substrate with a first CMP composition to remove residual copper containing materials and at least a portion of the barrier layer, and chemical mechanical polishing the substrate with a second CMP composition to selectively remove residual barrier layer.
In another aspect, the invention provides a method for planarizing a substrate surface, comprising providing a substrate comprising a dielectric layer with feature definitions formed therein, a barrier layer conformally deposited on the dielectric layer and in the feature definitions formed therein, and a copper containing material deposited on the barrier layer and filling the feature definitions formed therein, supplying a bulk polishing composition to the substrate, removing substantially excess copper containing material at a ratio of copper containing material to barrier layer between about 1:0 and about 1:0.01 by a polishing technique, supplying a first polishing composition to the substrate, removing residual copper containing materials and removing a portion of the barrier layer from the substrate at a ratio of copper containing material to barrier layer between about 2:1 and about 1:1 by a polishing technique, supplying a second polishing composition to the substrate, and removing residual barrier layer from the surface of the substrate at a ratio of barrier layer to copper containing material to dielectric layer between about 1:0:0 and about 1:0.2:0.2 by a chemical mechanical polishing technique.
Another aspect of the invention provides a method for planarizing a barrier layer comprising a tantalum containing material on a substrate surface, comprising chemical mechanical polishing the substrate to selectively remove residual copper containing material and a portion of the tantalum containing material therefrom, and then chemical mechanical polishing the substrate to selectively remove residual tantalum containing material therefrom.